IIT Kanpur Interview Experience - Microelectronics, VLSI & Display Technologies (2014)


This is the interview experience of Disha Shrivastava,which i had read  while looking for details on IIT Kanpur on her personal blog .
YEAR- 2014  (GATE ECE)
The list of shortlisted candidates for IIT Kanpur MTech interview was put up on the website. I had applied in three specializations at IIT Kanpur : 1) Microelectronics, VLSI & Display Technologies 2) Signal Processing & Communication 3) RF & Microwave in the same order of preference, but my name was appearing in only one list ( VLSI ) though my GATE score was above the cutoff in other two specializations as well. This outcome puzzled me and then I came to know the hard truth which was not revealed to me either by IIT Kanpur or anyone else while applying. At IIT Kanpur, they will shortlist you only for one specialization based on your order of preference and will interview you only in that specialization. You can’t even appear for the interview of other specializations even if your score is higher than its cutoff. So, friends be very careful while applying. Give preferences based both on your interests and the areas which you are strong in so that you can display your worth in the interviews.

I had stayed in IIT Kanpur for two months as part of my summer project after BE 2nd year. So, I was very much aware of the campus and the locations of each department. They had marked two days for the interview (6th – 7th May) which seemed justified when I entered a huge hall packed with students on 6th at 7 am. They had called around 350 students for interview of just one specialization ( VLSI )!! After 2-3 hours of confusion among the co-ordinators and growing impatience of the students, interviews were finally started. We were dispatched from the lecture hall in groups of 10 students to reach the Electrical Engg. Dept where interviews were being held. I learnt from the co-ordinators that there were 3 interview panels for VLSI each consisting of 2-3 professors.There was no fixed sequence of sending students inside. Everyone in the room had to catch a train at night and so order was changed based on their convenience ( Many people creating fake flights and trains). My name was 3rd in the list but thanks to our urgency friends, I was dropped down to 18th spot. In store for me were, yes you guessed it right a decade of waiting hours😦  To add to my irritation, profs. were conducting a single interview for 50-55 mins..Being tired both mentally and physically, finally my chance came at 7pm.
Interview:
There were two professors in my Panel. As soon as I entered the room they handled me a chalk and sent me to the blackboard adding to my anxiety. The questions which they asked were as follows:
  • Draw the drain current vs gate-to-source voltage curve for nMOS.
  • Write the equation for drain current ( asked what each parameter is in the equation)
  • What is mobility? Draw its graph showing its variation with temperature. Why does it show such a dependence. Explain.
  • Draw the circuit of a CMOS inverter. Justify the connections (i.e, why nmos substrate is connected to ground,etc.)
  • Draw Voltage Transfer Curve ( VTC ) of CMOS. How will the VTC change if pmos is replaced with a resistance.
  • What is switching threshold voltage? Derive an expression for it. How does it depend on W/L ratio?
  • Draw the VTC if W/L ratio of pmos is increased/decreased.
The interview lasted for about 45 mins. I answered 85% of the questions and they were satisfied with my explanations. Some of the questions were not of undergraduate level and they themselves said that they were not expecting me to answer them. Learning from my earlier mistake, I had studied some analog and devices portion before reaching Kanpur. At the end of the interview, I was quite happy with my performance (especially compared to previous one) and was relieved that now I can go home. I heard that all the interviews after me ( that day and the next day) were just 10-15 mins long ; so luck also favoured me in a way here. The results were out quite late ( May End) and I was selected with 36 other people:) ( Note: The intake at VLSI at iitk is roughly 12-13 ; but since they release only one list, they have to keep margin and thus make offer to more candidates).
Pros:
  • IIT Kanpur is known for its academics and is also quite reputed for being a good research institute (some say it is the 2nd best after IISc in research).
  • IITk mess offers the best food you can have in any of the IIT’s and IISc. The quality and the variety of food is pretty good. The act of hot rotis being served as soon as you finish the one on your plate and drinking water being changed periodically to ensure that it remains cold happens only in Kanpur J
  •  The campus is beautiful and very well maintained (as soon as a leaf falls on the road, it is swept off immediately ); good hostels with 24 hours functioning canteens; amazing playgrounds for almost all sports and dancing peacocks provide irresistible attractions:)
  • One thing which I liked very much and which I would like to mention is the attitude of the mess staff and security guards. They take care of you as a child and are always ready to help in a sincere and polite way.
Cons:
  • Apparently, the best specialization for EC at IITk is not Microelectronics & VLSI , its Signal Processing & Communication (I came to know about this later and this was one of the mistakes which I made while applying ) It is good both for research and placements. Surprisingly, the cut-off for Spcom was much lower than VLSI and its intake was also huge (70).
  • The academic system at iitk is quite stringent in the sense that you get only even grades (after 10 comes 8 then 6 ;which means there are no 9’s and 7’s). This affects your CGPA and can be a concerning factor if you are applying for PhD abroad.
  • According to the current batch students studying VLSI there, the faculty members in this course are very less and 90% of the research going on is in the field of Devices (which sadly doesn’t have much scope in India till now; but has wide opportunities abroad).To add to the grievances, were the below average placements in VLSI this year (This doesn’t mean that placements are always like this)

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